Several recently proposed microprocessor architectures provide increased performance through out-of-order andor speculative superscalar execution. These architectures are complex and may require changes to the instruction set. Alternatively, multi-threaded architectures attempt to increase pipeline utilization by concurrently executing instructions from different threads. This paper describes a multi-threaded superscalar architecture called Hobbes. In the proposed architecture, up to two instructions can be issued per cycle from any of the four on-board threads. Instructions are issued in-order, without branch prediction. It is argued that using multi-threading increases the available instruction-level parallelism without needing to support complex techniques such as out-of-order issue, register-renaming, branch prediction, and load by-passing of stores.
Results from trace-driven simulations of the architecture are presented. It is shown that, with similar execution, cache and memory resources, Hobbes can provide better performance than a more complex, out-of-order, superscalar processor.
Copyright 1994 by Bradley J. Kish and Bruno R. Preiss.
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